1. Field of the Invention
This invention relates to bipolar transistors and semiconductor devices and, more particularly, to a bipolar transistor lowered in collector-to-emitter saturation voltage VCE(sat) and a semiconductor device formed with such a bipolar transistor and a MOS transistor on a same substrate.
2. Description of the Related Art
There is shown, in FIG. 5, a structure of a semiconductor device in an related art formed with NPN and NMOS transistors on a same substrate. FIG. 5A is a plan view while FIG. 5B is a sectional view of the same.
An NPN transistor 80 includes an N+ buried layer 82 formed of As (arsenic), Sb (antimony) or the like in a P-type silicon substrate 81, a collector region 83 formed thereon by an N−layer, a base region 84 formed by a P−layer in the collector region 83, and an emitter region 85 formed by an N layer in the base region 84. In the collector region 83, a collector wall 86 is formed by an N+ layer diffused with P (phosphorus). In the collector wall 86, a collector contact region 87 is formed by an N+ layer diffused with As in the contact wall 86. A collector electrode 88 is connected to a surface of the collector contact region 87. The collector wall 86 is provided in order to lower the collector series resistance of the NPN transistor 80, to reduce the collector-to-emitter saturation voltage VCE(sat). A base electrode 91 is connected to the base region 84 through a P+-layered base contact region 89. An emitter electrode 93 is connected to the emitter region 85 through an emitter contact region 92. The reference 94 represents a device-isolation oxide layer (LOCOS) while the reference 95 shows an insulation film.
The NMOS transistor 90 includes a source region 96 and drain region 97 formed by an N+ layer diffused with As in the P-type silicon substrate 81, and a gate electrode 99 formed by an SiO2 film through a gate insulation film 98 on an intermediate region between the source region 96 and the drain region 97. In the periphery of the gate electrode 99, an N− LDD region 100 is formed by diffusion with P (phosphorus). A source electrode 101 is connected to the source region 96, while a drain electrode 102 is connected to the drain region 97.
As described above, the NPN transistor 80 of the related-art semiconductor device has a collector wall 86 for the purpose of lowering the collector-to-emitter saturation voltage VCE(sat). The collector wall 86, being formed deeper as reaching the buried layer 82 by the thermal diffusion of a high concentration impurity, is likely to spread laterally over a broad range. This increases spacing between the collector electrode 88 and the base electrode 91, resulting in a problem of increased transistor size. Meanwhile, in order to form a collector wall 86 to such a depth as reaching the buried layer 82, there is a need of a thermal diffusion process exclusive for forming a collector wall 86. Thus, there arises a problem of incurring the increase in the number of processes for an NPN transistor 80 and, eventually, a semiconductor device having NPN transistors 80.